Gem5模拟器学习（二）

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理解gem5的输出

本文是对官网教程gem5: Understanding gem5 statistics and output的整理，主要介绍了gem5的输出文件

模拟输出默认存放在m5out文件夹中，也可通过-d dirname命令行选项控制输出文件夹，但注意该选项只能在gem5.opt和配置脚本之间。例如

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build/X86/gem5.opt -d cache_out configs/learning_gem5/part1/two_level.py

模拟系统会自动在当前文件夹下创建一个cache_out文件夹，并存放所用输出数据

输出如下

1. config.ini

模拟系统的全部配置参数

2. config.json

模拟系统的全部配置参数，json文件格式

3. stats.txt

模拟过程的数据统计。

SimObject的每个实例化都有自己的统计信息。模拟结束时，或发出特殊统计转储命令时，所有SimObjects的统计信息的当前状态都会转储到一个文件中。

统计转储以—————-开始模拟统计—————-开始。如果在gem5执行期间存在多个统计转储，则单个文件中可能存在多个此类转储。这对于长时间运行的应用程序或从检查点恢复时很常见。

每个统计信息都有一个名称（第一列）、一个值（第二列）和一个描述（最后一列以#开头），后跟统计信息的单位。

（1）有关执行的一般统计信息：

首先，统计信息文件包含有关执行的一般统计信息：

比如总模拟时间simSeconds，CPU提交的指令数simInsts

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---------- Begin Simulation Statistics ----------
simSeconds                                   0.000057                       # Number of seconds simulated (Second)
simTicks                                     57467000                       # Number of ticks simulated (Tick)
finalTick                                    57467000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq                                  1000000000000                       # The number of ticks per simulated second ((Tick/Second))
hostSeconds                                      0.03                       # Real time elapsed on the host (Second)
hostTickRate                               2295882330                       # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory                                     665792                       # Number of bytes of host memory used (Byte)
simInsts                                         6225                       # Number of instructions simulated (Count)
simOps                                          11204                       # Number of ops (including micro ops) simulated (Count)
hostInstRate                                   247382                       # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate                                     445086                       # Simulator op (including micro ops) rate (op/s) ((Count/Second))

---------- Begin Simulation Statistics ----------
simSeconds                                   0.000490                       # Number of seconds simulated (Second)
simTicks                                    490394000                       # Number of ticks simulated (Tick)
finalTick                                   490394000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq                                  1000000000000                       # The number of ticks per simulated second ((Tick/Second))
hostSeconds                                      0.03                       # Real time elapsed on the host (Second)
hostTickRate                              15979964060                       # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory                                     657488                       # Number of bytes of host memory used (Byte)
simInsts                                         6225                       # Number of instructions simulated (Count)
simOps                                          11204                       # Number of ops (including micro ops) simulated (Count)
hostInstRate                                   202054                       # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate                                     363571                       # Simulator op (including micro ops) rate (op/s) ((Count/Second))

（2）SimObjects的统计信息

接下来，将打印SimObjects的统计信息，比如CPU、内存控制器等等

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system.clk_domain.clock                          1000                       # Clock period in ticks (Tick)
system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts (Volt)
system.cpu.numCycles                            58236                       # Number of cpu cycles simulated (Cycle)
system.cpu.numWorkItemsStarted                      0                       # Number of work items this cpu started (Count)
system.cpu.numWorkItemsCompleted                    0                       # Number of work items this cpu completed (Count)
system.cpu.dcache.demandHits::cpu.data           1951                       # number of demand (read+write) hits (Count)
system.cpu.dcache.demandHits::total              1951                       # number of demand (read+write) hits (Count)
system.cpu.dcache.overallHits::cpu.data          1951                       # number of overall hits (Count)
system.cpu.dcache.overallHits::total             1951                       # number of overall hits (Count)
system.cpu.dcache.demandMisses::cpu.data          136                       # number of demand (read+write) misses (Count)
system.cpu.dcache.demandMisses::total             136                       # number of demand (read+write) misses (Count)
...
...
...
system.mem_ctrl.avgPriority_cpu.inst::samples       228.00                       # Average QoS priority value for accepted requests (Count)
system.mem_ctrl.avgPriority_cpu.data::samples       136.00                       # Average QoS priority value for accepted requests (Count)
system.mem_ctrl.priorityMinLatency       0.000000018750                       # per QoS priority minimum request to response latency (Second)
system.mem_ctrl.priorityMaxLatency       0.000000489500                       # per QoS priority maximum request to response latency (Second)
system.mem_ctrl.numReadWriteTurnArounds             0                       # Number of turnarounds from READ to WRITE (Count)
system.mem_ctrl.numWriteReadTurnArounds             0                       # Number of turnarounds from WRITE to READ (Count)
system.mem_ctrl.numStayReadState                  742                       # Number of times bus staying in READ state (Count)
system.mem_ctrl.numStayWriteState                   0                       # Number of times bus staying in WRITE state (Count)
system.mem_ctrl.readReqs                          364                       # Number of read requests accepted (Count)
system.mem_ctrl.writeReqs                           0                       # Number of write requests accepted (Count)
system.mem_ctrl.readBursts                        364                       # Number of controller read bursts, including those serviced by the write queue (Count)
system.mem_ctrl.writeBursts                         0                       # Number of controller write bursts, including those merged in the write queue (Count)

安装python的Pydot包之后，当运行gem5进行模拟仿真之后，即可在m5out目录下找到config.pdf之类的配置图,如图1所示。

还可以通过dot命令将config.dot文件转换成自己需要的格式

pip install pydot
cd m5out
dot -Tpng -o config.png config.dot

RISCV1024核模拟报错